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8-Channel 45V 50mA LED Driver
ISL97678
The ISL97678 is an 8-channel PWM dimming LED driver for LCD backlight applications. The ISL97678 is capable of driving up to 96 pieces of 3.4V/50mA LEDs but larger numbers of LEDs is possible if the LED forward voltage combined is less than 45V. The ISL97678 has 8 channels of voltage controlled current sources with typical currents matching to 1%, which compensate for the non-uniformity effect of forward voltages variance in the LED strings. To minimize the voltage headroom and power loss in the typical multi-string operation, the ISL97678 features dynamic headroom control that monitors the highest LED forward voltage string and uses its feedback signal for output regulation. The ISL97678 features PWM dimming up to 30kHz with 0.8%~100% duty cycle and maintains 1% current matching across all ranges. The PWM dimming frequency can be adjusted between 100Hz and 30kHz. The boost switching frequency can also be adjusted between 600kHz and 1.5MHz. The ISL97678 features extensive protection functions that include string open and short circuit detections, OVP, and OTP. ISL97678 is available in the 32 Leads QFN 5mmx5mm and operate from -40C to +85C with input voltage ranges from 4.75V to 26V.
ISL97678
Features
* 8 Channels * 4.75V ~ 26V Input * 45V Maximum Output * Drive Typically 96 LEDs (3.4V/50mA each) * External PWM Input up to 25kHz Dimming * Dimming range 0.8%~100% up to 30kHz * Current Matching 0.7% * Protections - String Open Circuit and Short Circuit Detections, OVP, and OTP * Adjustable Dimming Frequency * Adjustable Switching Frequency * 32 Ld (5mmx5mm) QFN Package
Applications
* Notebook Displays WLED or RGB LED Backlighting * LCD Monitor LED Backlighting
November 5, 2009 FN6998.1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97678
Typical Application Circuit
VIN* = 4.75V~26V Ci 10uF
16
L1 10uH/3A
D1 Co 3x4.7uF
8x12 = 96 LEDs Output 45V*, 50mA per string max
ISL97678
LX1 20 VIN VDC VLOGIC OVP
23
LX2 21
806k 100pF 22k 3.3nF
1uF 1uF
18 10
4 17 14
PWM EN COMP RSET FSW FPWM AGND AGND AGND AGND AGND AGND AGND AGND PGND PGND
1 19
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
25 26 27 28 29 30 31 32
3.3nF
14.2k 13 11 12 333k 2 3 6 7 8 9 5 15
15k
50k
* Vin > = 12V for 45V/50mA Applications
PGND 22
FIGURE 1. ISL97678 TYPICAL APPLICATION DIAGRAM
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Block Diagram
VIN* = 4.75V~26V 10uH/3A VIN VDC VLOGIC EN Analog Bias Logic Bias
Fault
45V*, 50mA per string 96 (8x12) LEDs 2x4.7uF/50V
LX O/P Short
REG1 REG2 OSC & RAMP Comp
OVP
Boost SW
OVP
fsw
fSW
=0
Imax
ILIMIT
Logic
FET Drivers
PGND
p e
Fault Control
COMP
GM AMP
Open Ckt, Short Ckt Detects
Highest VF String Detect
VSET + -
CH1 CH2 CH8
1
Temp Sensor
Fault Control
RSET
+ -
REF GEN
+ -
AGND
REF_OVP REF_VSC
2
PWM fPWM PWM Dimming Controller
+ -
* Vin >=12V for 45V/50mA apps 8
ISL97678
FIGURE 2. ISL97678 BLOCK DIAGRAM
Ordering Information
PART NUMBER ISL97678IRZ (Notes 1, 2) NOTES: 1. Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97678. For more information on MSL please see techbrief TB363. PART MARKING ISL9767 8IRZ PACKAGE (Pb-free) 32 Ld 5x5 QFN PKG. DWG. # L32.5x5B
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Pin Configuration
ISL97678 (32 LD 5X5 QFN) TOP VIEW
CH8 CH7 CH6 CH5 CH4 CH3 CH2 26 CH1 25 24 NC 23 OVP 22 PGND 21 LX EXPOSED THERMAL PAD AGND AGND AGND AGND 5 6 7 8 9 AGND 10 VLOGIC 11 FSW 12 FPWM 13 RSET 14 COMP 15 AGND 16 VIN 20 LX 19 PGND 18 VDC 17 EN
32 PGND AGND AGND PWM 1 2 3 4
31
30
29
28
27
Pin Descriptions
PIN 1, 19, 22 2, 3, 5, 6, 7, 8, 9, 15 4 10 11 12 13 14 16 17 18 20, 21 23 24 25 ~ 32 NAME PGND AGND PWM VLOGIC FSW FPWM RSET COMP VIN EN VDC LX OVP NC CH1 ~ CH8 S S I O I I I O S I S O I
(I = Input, O = Output, S = Supply) DESCRIPTION Power Ground Analog Ground PWM Brightness Control Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation When RFSW is 100k, fSW is 500kHz. When RFSW is 33k, fSW is 1.5MHz When RFPWM is 333k, FPWM is 200Hz. When RFPWM is 3.3k, FPWM is 20kHz. Resistor Connection for Setting LED Current Boost compensation Main Power Enable Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation Boost MOSFET Drain Terminal Switching Node Overvoltage Protection Input as well as Output Voltage FB Monitoring No Connect LED Driver PWM Dimming Monitoring
TYPE
I/O I
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Absolute Maximum Ratings
Voltage ratings are all with respect to AGND pin VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V VDC, PWM . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . -0.3V to min . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VDC + 0.3V, 5.75V) CH1 - CH8, LX, OVP . . . . . . . . . . . . . . . . . . . . -0.3V to 45V PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 3 PSIJT (C/W) 32 Ld QFN (Notes 4, 5) . . . . . . . . . 31 Thermal Characterization (Typical, Note 6)
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40C to +85C
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 Maximum Continuous Junction Temperature . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Power Dissipation TA < +25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W TA < +70C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W TA < +85C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W TA < +100C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings.
Electrical Specifications
5.
All specifications below are characterized at TA = -40C to +85C; VIN = 12V, /SHUT = 5V, ISET = 36k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. DESCRIPTION CONDITION MIN (Note 7) TYP MAX (Note 7) UNIT
PARAMETER GENERAL VIN IVIN_SHDN VOUT VUVLO VUVLO_HYS
Backlight Supply Voltage VIN Shutdown Current Output Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis /SHUT = 0
4.75
26 (Note 8) 5 45
V A V V mV
2.9 300
3.3
LINEAR REGULATOR VDC VDC_DROP IVDC VLOGIC VLOGIC_DROP 5V Analog Bias Regulator VDC LDO Dropout Voltage Active Current 2.5V Logic Bias Regulator VLOGIC LDO Dropout Voltage VIN > 6V IVDC = 30mA /SHUT = 5V, R = 33k VIN > 6V IVLOGIC = 30mA 2.3 4.8 5 71 10 2.4 31 2.5 100 5.1 100 V mV mA V mV
BOOST SWITCHING REGULATOR SS SWILimit rDS(ON) Soft-Start Boost FET Current Limit Internal Boost Switch ON-Resistance TA = +25C to +85C 3.0 130 16 4.7 ms A m
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Electrical Specifications
All specifications below are characterized at TA = -40C to +85C; VIN = 12V, /SHUT = 5V, ISET = 36k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) DESCRIPTION Peak Efficiency CONDITION VIN = 24V, 96LEDs, 20mA each, L = 10H with DCR 100m, FSW = 600kHz, TA = +25C VIN = 12V, 96 LEDs, 20mA each, L = 10H with DCR 100m, FSW = 600kHz, TA = +25C VIN = 6V, 96 LEDs, 20mA each, L = 10H with DCR 100m, FSW = 600kHz, TA = +25C VIN = 24V, 80 LEDs, 40mA each, L = 10H with DCR 100m, FSW=600kHz, TA = +25C VIN = 12V, 80 LEDs, 40mA each, L = 10H with DCR 100m, FSW = 600kHz, TA = +25C DMAX DMIN fSW Boost Maximum Duty Cycle Boost Minimum Duty Cycle Boost Switching Frequency fSW = 500kHz fSW = 500kHz Rfsw = 100k Rfsw = 33k ILX_leakage REFERENCE IMATCH IACC Channel-to-Channel Current Matching Absolute Current Accuracy ILED = 20mA IRSET = 36k, TA = +25C IRSET = 36k, TA = -40C to +80C FAULT DETECTION VSC Vtemp Vtemp_acc VOVP Channel Short Circuit Threshold Over-Temperature Threshold Over-Temperature Threshold Accuracy Overvoltage Limit on OVP Pin 1.18 3.3 150 5 1.22 1.24 4.6 V C C V -1.1 -1.5 -2 0.7 +1.1 +1.5 +2 % % % Lx Leakage Current VLX = 45V, /SHUT = 0V 0.45 1.35 0.5 1.5 90 10 0.55 1.65 10 MIN (Note 7) TYP 92.4 MAX (Note 7) UNIT %
PARAMETER Eff_peak
91.5
%
81.6
%
93.4
%
90.7
%
% % MHz MHz A
DIGITAL INTERFACE VIL VIH Logic Input Low Voltage Logic Input High Voltage 1.5 0.8 5.5 V V
CURRENT SOURCES VHEADROOM Dominant Channel Current Source Headroom at CH Pin ILED = 50mA TA = +25C 1.0 V
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Electrical Specifications
All specifications below are characterized at TA = -40C to +85C; VIN = 12V, /SHUT = 5V, ISET = 36k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) DESCRIPTION Voltage at ISET Pin Maximum LED Current per Channel LED config = 8P10S with VF = 3.4V and VIN = 11V CONDITION MIN (Note 7) 1.18 TYP 1.21 50 MAX (Note 7) 1.24 UNIT V mA
PARAMETER VISET ILEDmax
PWM GENERATOR FPWM Generated PWM Frequency RFPWM = 330k RFPWM = 3.3k Dimming Range VFSW FPWMI VFPWM NOTES: 7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. At maximum VIN of 26V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN 9. Limits established by characterization and are not production tested. PWM Dimming Duty Cycle Limits (Note 9) fSW Voltage PWMI Input Frequency Range (Note 9) VFPWM Voltage RFPWM = 3.3k fPWM 30kHz RFSW = 33k 180 18 0.4 1.18 200 1.18 1.21 1.21 200 20 220 22 100 1.24 20k 1.25 Hz kHz % V Hz V
Typical Performance Curves
100 95 EFFICIENCY (%) 90 85 80 75 70 +25C 50mA 8P11S fSW = 600kHz EFFICIENCY (%) 0C +85C -40C 100 95 90 85 80 75 70 20mA 8P11S fSW = 600kHz 0C +85C -40C
+25C 0 5 10 15 VIN (V) 20 25 30
0
5
10
15 VIN (V)
20
25
30
FIGURE 3. EFFICIENCY vs VIN vs TEMPERATURE AT 50mA
FIGURE 4. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA
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Typical Performance Curves (Continued)
100 95 90 85 80 75 70 65 60 55 50 45 40 35 30
95
8P10S
94 93
EFFICIENCY (%) 12V/50mA
50mA 8P11S
EFFICIENCY (%)
92 91 90 89 88 87 86 85 84 400
24V
24V/50mA
12V
0
10
20 30 ILED (mA)
40
50
600 800 1k 1.2k 1.4k SWITCHING FREQUENCY (Hz)
1.6k
FIGURE 5. EFFICIENCY vs ILED
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY
1.0 CURRENT MATCHING (%) 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
CURRENT MATCHING (%)
20mA - 8P12S 50mA - 8P11S 12V/20mA
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0
50mA 8P11 0C
+25C +85C
12V/50mA
-40C 5 10 15 VIN (V) 20 25 30
1
2
3
4 5 CHANNEL
6
7
8
FIGURE 7. CHANNEL-TO-CHANNEL CURRENT MATCHING EXAMPLE
FIGURE 8. CURRENT MATCHING vs VIN vs TEMPERATURE
2.0 1.8 1.6 1.4 ILED (mA) 1.2 1.0 0.8 0.6 0.4 0.2 24V/20mA 5V/20mA 20mA - 8P12S 50mA - 8P11S 12V/50mA 24V/50mA CHANNEL VOLTAGE (V)
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1 2 12V/20mA 12V/50mA
20mA - 8P12S 50mA - 8P11S
HEADROOM CONTROL CHANNEL 3 4 5 CHANNEL 6 7 8
0.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 PWM DIMMING DUTY CYCLE (%)
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE
FIGURE 10. TYPICAL CHANNEL VOLTAGE EXAMPLE
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Typical Performance Curves (Continued)
1.00 0.95 0.90 VHEADROOM (V) VHEADROOM (V) 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0 5 10 15 VIN (V) 20 25 30 0C +85C 50mA 8P11S 1.0 +25C 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 5 10 15 VIN (V) 20 25 30 +25C 0C 20mA 8P11S +85C
FIGURE 11. VHEADROOM vs VIN vs TEMPERATURE AT 50mA
FIGURE 12. VHEADROOM vs VIN vs TEMPERATURE AT 20mA
10 9 8 IIN (mA) 7 6 5 4 3 2 1 0 0
/SHUT = HIGH PWM DUTY CYCLE = 0% LX (20V/DIV) +85C VO (100mV/DIV) -40C ILED (20mA/DIV)
5
10
15 VIN (V)
20
25
30
FIGURE 13. QUIESCENT CURRENT vs VIN vs TEMPERATURE WITH /SHUT ENABLE
FIGURE 14. VOUT RIPPLE VOLTAGE
VO (20V/DIV) EN (5V/DIV)
VO (20V/DIV) EN (5V/DIV)
IIN (1A/DIV) IIN (1A/DIV)
ILED (50mA/DIV)
ILED (50mA/DIV)
FIGURE 15. IN-RUSH CURRENT and LED CURRENT AT VIN = 12V
FIGURE 16. IN-RUSH CURRENT AND LED CURRENT AT VIN = 26V
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Typical Performance Curves (Continued)
VIN (10V/DIV) VIN (10V/DIV) IIN (500mA/DIV) IIN (500mA/DIV)
ILED (50mA/DIV)
ILED (50mA/DIV)
FIGURE 17. LINE REGULATION WITH VIN CHANGES FROM 12V TO 26V DISABLE PROFILE
FIGURE 18. LINE REGULATION WITH VIN CHANGES FROM 26V TO 12V
VO (1V/DIV) VO (1V/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 19. LOAD REGULATION WITH ILED CHANGES FROM 0.4% TO 100% PWM DIMMING
FIGURE 20. LOAD REGULATION WITH ILED CHANGES FROM 100% TO 0.4% PWM DIMMING
VO (1V/DIV)
VO (500mV/DIV)
ILED (20mA/DIV) ILED (20mA/DIV)
FIGURE 21. LOAD REGULATION WITH ILED CHANGES FROM 0% TO 100% PWM DIMMING
FIGURE 22. LOAD REGULATION WITH ILED CHANGES FROM 100% to 0% PWM DIMMING
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Typical Performance Curves (Continued)
VO (20V/DIV) EN (5V/DIV)
IIN (1A/DIV)
ILED (50mA/DIV)
FIGURE 23. DISABLE PROFILE
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal voltage needed to enable the LED string with the highest forward voltage drop to run at the programmed current. The ISL97678 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. Such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be several Li-ion cell batteries or instantly change to an AC/DC adapter without rendering a noticeable visual nuisance. The number of LEDs that can be driven by ISL97678 depends on the type of LED chosen in the application. The ISL97678 is capable of boosting up to 45V and drive 8 channels of LEDs at maximum of 45mA per channel.
.
+ RSET
+ REF
+ PWM DIMMING
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current source circuit, as shown in Figure 24. The LED peak current is set by translating the RSET current to the output with a scaling factor of 707.9/RSET. The source terminals of the current source MOSFETs are designed to run at 500mV to optimize power loss versus accuracy requirements. The sources of errors of the channel-to-channel current matching come from the op amps offset, internal layout, reference, and current source resistors. These parameters are optimized for current matching and absolute current accuracy. However, the absolute accuracy is additionally determined by the external RSET. A 0.1% tolerance resistor is recommended.
FIGURE 24. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97678 features a proprietary Dynamic Headroom Control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the CH pins. When this lowest IIN voltage is lower than the short circuit threshold, VSC, such voltage will be used as the feedback signal for the boost regulator. The boost makes the output to the correct level such that the lowest CH pin is at the target headroom voltage. Since all LED strings are connected to the same output voltage, the other CH pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same programmed current. The output voltage will regulate cycle-by-cycle and is always referenced to the highest forward voltage string in the architecture.
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OVP and VOUT Requirement
The Overvoltage Protection (OVP) pin has a function of setting the overvoltage trip level as well as limiting the VOUT regulation range. The ISL97678 OVP threshold is set by RUPPER and RLOWER as shown in Equation 1:
V OUT_OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 1)
PWM Dimming Frequency Adjustment
The dimming frequencies are set by an external resistor at the FPWM pin as shown by Equation 3:
6.66 x10 f PWM = ----------------------RPWM
7
(EQ. 3)
where fPWM is the desirable PWM dimming frequency and RFPWM is the setting resistor.
VOUT can only regulate between 64% and 100% of the VOUT_OVP such that: Allowable VOUT = 64% to 100% of VOUT_OVP For example, if 10 LEDs are used with the worst case VOUT of 35V. If R1 and R2 are chosen such that the OVP level is set at 40V, then the VOUT is allowed to operate between 25.6V and 40V. If the requirement is changed to a 6 LEDs 21V VOUT application, then the OVP level must be reduced and users should follow VOUT = (64% ~100%)OVP requirement. Otherwise, the headroom control will be disturbed such that the channel voltage can be much higher than expected and sometimes it can prevents the driver from operating properly. The ratio of the OVP capacitors should be the inverse of the OVP resistors. For example, if RUPPER/RLOWER= 33/1, then CUPPER/CLOWER=1/33 with CUPPER = 100pF and CLOWER = 3.3nF.
Switching Frequency
The boost switching frequency can be adjusted by a resistor as shown in Equation 4:
( 5 x10 ) f SW = ----------------------R OSC
10
(EQ. 4)
where fSW is the desirable boost switching frequency and ROSC is the setting resistor.
5V and 2.3V Low Dropout Regulators
A 5V LDO regulator is present at the VDC pin to develop the necessary low voltage supply, which is used by the chips internal control circuitry. Because VDC is an LDO pin, it requires a bypass capacitor of 1F or more for the regulation. The VDC pin can be used for a coarse regulator or reference but do not pull more than few mA from it. Similarly, a 2.3V LDO regulator is present at the VLOGIC pin to develop the necessary low voltage supply for the chip's internal logic control circuitry. A 1F bypass capacitor or more is needed for regulation. The VLOGIC pin can be used as a coarse regulator or reference but do not pull more than few mA from it.
Dimming Controls
The ISL97678 allows two ways of controlling the LED current, and therefore, the brightness. They are: 1. DC current adjustment 2. PWM chopping of the LED current defined in Step 1. There are various ways to achieve DC or PWM current control, which will be described in the following. In any dimming controls, the EN pin must be high. EN is a high voltage pin that can be applied with a digital signal or tied directly to VIN for enable function. MAXIMUM DC CURRENT SETTING The initial brightness should be set by choosing an appropriate value for RSET. This should be chosen to fix the maximum possible LED current:
707.9 I LEDmax = -------------R SET (EQ. 2)
Soft-Start
The ISL97678 uses a digital soft-start where the boost current limit is stepped up in 8 steps. The initial current limit level is set to one ninth of the full current limit, with subsequent steps increasing this by a ninth every 2ms. In the event that no LEDs have been conducting during the interval since the last step (for example if the LEDs are running at low duty cycle at low PWM frequency) then the step will be delayed until the LEDs are conducting. If the LEDs are disabled and re-enabled again then soft start will be restarted when the LEDs are enabled.
Fault Protection and Monitoring
The ISL97678 features extensive protection functions to cover all the perceivable failure conditions. The failure mode of a LED can be either open circuit or as a short. The behavior of an open circuited LED can additionally take the form of either infinite resistance or, for some LEDs, a zener diode, which is integrated into the device in parallel with the now opened LED. For basic LEDs (which do not have built-in zener diodes), an open circuit failure of an LED will only result in the loss of one channel of LEDs without affecting other channels. Similarly, a short circuit condition on a channel that
Alternatively, the RSET can be replaced by a digital potentiometer for adjustable current. PWM CONTROL The ISL97678 provides PWM dimming by PWM chopping of the current in the LEDs for all 8 channels. To achieve PWM dimming, the users need to apply a PWM signal at the PWM pin. The PWM output will follow the PWM input and the dimming frequency will be set by RPWM. During the On periods, the LED current will be defined by the value of RSET, as described in Equation 1. 12
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results in that channel being turned off does not affect other channels unless a similar fault is occurring. Due to the lag in boost response to any load change at its output, certain transient events (such as significant step changes in LED duty cycle) can transiently look like LED fault modes. The ISL97678 uses feedback from the LEDs to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the LED strings to fault out. See Table 1 for more details.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps the voltage at a safe level. The OVP threshold is set as shown in Equation 5:
OVP = 1.21V x ( RUPPER + R LOWER ) R LOWER (EQ. 5)
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold. When an LED becomes shorted, the action taken is described in Table 1. The short circuit threshold is 4V.
These resistors should be large to minimize the power loss. For example, a 1Mk RUPPER and 30k RLOWER sets OVP to 41.2V. Large OVP resistors also allow COUT discharges slowly during the PWM Off time. Parallel capacitors should be placed across the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER. Using a CUPPER value of at least 30pF is recommended. These capacitors reduce the AC impedance of the OVP node, which is important when using high value resistors.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.8V, the device will stop switching and be reset. Operation will restart only if the device control interface re-enables it once the input voltage is back in the normal operating range. Also all digital settings will be reset to their default states.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. The ISL97678 monitors the current in each channel such that any string which reaches the intended output current is considered "good". Should the current subsequently fall below the target, the channel will be considered an "open circuit". Furthermore, should the boost output of the ISL97678 reach the OVP limit or should the lower over-temperature threshold be reached, all channels which are not "good" will immediately be considered as "open circuit". Detection of an "open circuit" channel will result in a time-out before disabling of the affected channel. Some users employ some special types of LEDs that have zener diode structure in parallel with the LED for ESD enhancement, thus enabling open circuit operation. When this type of LED goes open circuit, the effect is as if the LED forward voltage has increased, but no light will be emitted. Any affected string will not be disabled, unless the failure results in the boost OVP limit being reached, allowing all other LEDs in the string to remain functional. Care should be taken in this case that the boost OVP limit and SCP limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. This is due to the increased forward voltage of the faulty channel making all other channel look as if they have LED shorts. See Table 1 for details for responses to fault conditions.
Over-Temperature Protection (OTP)
The ISL97678 includes two over-temperature thresholds. The lower threshold is set to +130C. When this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as "open circuit" and disabled after a time-out period. The intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. The upper threshold is set to +150C. Each time this is reached, the boost will stop switching and the output current sources will be switched off and stay off until the control driver is power off and and re-enables it. Also unless disabled via the /SHUT pin, the device stays in an active state throughout. For the extensive fault protection conditions, please refer to Figure 25 and Table 1 for details.
Shutdown
When the EN pin is low the entire chip is shut down to give close to zero shutdown current. The digital interfaces will not be active during this time.
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ISL97678
VIN LX O/P SHORT FET DRIVER OVP VOUT
FAULT DRIVER
IMAX
ILIMIT
LOGIC
VSC
CH1
VSET/2 REG
CH8
THRM SHDN
REF T2 TEMP SENSOR T1 VSET + Q1 VSET + PWM8/OC8/SC8 Q8
OTP
PWM1/OC1/SC1 CONTROL LOGIC
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS TABLE 1. PROTECTIONS TABLE VOUT REGULATED BY Highest VF of CH2 through CH8
CASE 1
FAILURE MODE CH1 Short Circuit
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION CH2 through CH8 Normal
Upper CH1 ON and burns power Over-Temperature Protection limit (OTP) not triggered and VIIN0 < VSC Upper OTP triggered but VIN1 < VSC Upper OTP not triggered but VIIN1 > VSC Upper OTP not triggered and VIIN1 < VSC CH1 goes off
2
CH1 Short Circuit
Same as CH1
Highest VF of CH2 through CH8
3
CH1 Short Circuit
CH1 disabled after 6 PWM cycles time-out.
Highest VF of If 3 channels are already shut down, all channels will CH2 through CH8 be shut down. Otherwise CH2-8 will remain as normal Highest VF of CH2 through CH8 VF of CH1
4
CH1 Open Circuit with infinite resistance CH1 LED Open Circuit but has paralleled Zener CH1 LED Open Circuit but has paralleled Zener
VOUT will ramp to OVP. CH1 will CH2 through CH8 Normal time-out after 6 PWM cycles and switch off. VOUT will drop to normal level. CH2 through CH8 ON, Q2 through Q8 burn power Same as CH1
5
Upper OTP not CH1 remains ON and has triggered and VIIN1 < highest VF, thus VOUT VSC increases Upper OTP triggered but VIIN1 < VSC CH1 goes off
6
VF of CH1
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ISL97678
TABLE 1. PROTECTIONS TABLE (Continued) VOUT REGULATED BY Highest VF of CH2 through CH8 VF of CH1
CASE 7
FAILURE MODE CH1 LED Open Circuit but has paralleled Zener
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION CH2 through CH8 Normal
CH1 OFF Upper OTP not triggered but VIIN1 > VSC CH1 remains ON and has Upper OTP not triggered but VIINx > highest VF, thus VOUT VSC increases.
VOUT increases then CH-X switches OFF. This is an unwanted shut off and can be prevented by setting OVP and/or VSC at an appropriate level.
8
Channel-toChannel VF too high Channel-toChannel VF too high Output LED string voltage too high VOUT/LX shorted to GND
Lower OTP triggered but VIINx < VSC
Any channel at below the target current will fault out after 6 PWM cycles. Remaining channels driven with normal current. All channels switched off
Highest VF of CH1 through CH8 Highest VF of CH1 through CH8 Highest VF of CH1 through CH8
9
Upper OTP triggered but VIINx < VSC
10
VOUT > VOVP
Driven with normal current. Any channel that is below the target current will time-out after 6 PWM cycles. LX will not switch
11
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FN6998.1 November 5, 2009
ISL97678
Components Selections
According to the inductor Voltage-Second Balance principle, the change of inductor current during the switching regulator On-time is equal to the change of inductor current during the switching regulator Off-time. Since the voltage across an inductor is as shown in Equation 6:
V L = L x I L t (EQ. 6)
offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. It is recommended that an input capacitor of at least 10F be used. Ensure the voltage rating of the input capacitor is suitable to handle the full supply range.
Inductor
The selection of the inductor should be based on its maximum and saturation current (ISAT) characteristics, power dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. Inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. The inductor's maximum current capability must be adequate enough to handle the peak current at the worst case condition. Additionally, if an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. The series resistance, DCR, within the inductor causes conduction loss and heat dissipation. A shielded inductor is usually more suitable for EMI susceptible applications, such as LED backlighting. The peak current can be derived from the voltage across the inductor during the Off-period, as expressed in Equation 10:
IL peak = ( V O x I O ) ( 85% x V I ) + 1 2 [ V I x ( V O - V I ) ( L x V O x f SW ) (EQ. 10)
and IL @ On = IL @ Off, therefore:
( V I - 0 ) L x D x tS = ( VO - VD - VI ) L x ( 1 - D ) x tS (EQ. 7)
where D is the switching duty cycle defined by the turn-on time over the switching periods. VD is Schottky diode forward voltage that can be neglected for approximation. Rearranging the terms without accounting for VD gives the boost ratio and duty cycle respectively as Equations 8 and 9:
VO VI = 1 ( 1 - D ) D = ( VO - VI ) VO (EQ. 8) (EQ. 9)
Input Capacitor
Switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. This reduces interaction between the regulator and input supply, thereby improving system stability. The high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. A capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as X5R or X7R ceramic capacitors, which
The choice of 85% is just an average term for the efficiency approximation. The first term is the average current, which is inversely proportional to the input voltage. The second term is the inductor current change, which is inversely proportional to L and fSW. As a result, for a given switching.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 11/5/09 10/26/09 REVISION FN6998.1 FN6998.0 CHANGE Changed VSC spec from Changed VSC spec from "3.3min, 4.4max" to "3.3min, 4.6max". Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL97678 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN6998.1 November 5, 2009
ISL97678
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07
4X 3.5 5.00 A B 6 PIN 1 INDEX AREA 28X 0.50 6 PIN #1 INDEX AREA
25 24
32 1
5.00
3 .30 0 . 15
17
(4X) 0.15 16 9
8
0.10 M C A B 4 32X 0.23 - 0.05
+ 0.07
32X 0.40 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1
C
BASE PLANE
SEATING PLANE 0.08 C
( 4. 80 TYP ) ( 3. 30 )
( 28X 0 . 5 )
SIDE VIEW
(32X 0 . 23 )
C ( 32X 0 . 60)
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6998.1 November 5, 2009

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